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MAKE(1) General Commands Manual MAKE(1)

make — maintain program dependencies

make [-BeiknpqrSst] [-C directory] [-D variable] [-d flags] [-f mk] [-I directory] [-j max_jobs] [-m directory] [-V variable] [NAME=value ...] [target ...]

make is a program designed to simplify the maintenance of other programs. Its input is a makefile: a list of specifications (target rules) describing build relationships between programs and other files. By default, the file makefile is used; if no such file is found, it tries Makefile. If neither of these exist, make can still rely on a set of built-in system rules.

If the file ‘.depend’ exists, it will also be read after the main makefile (see mkdep(1)).

The handling of ‘.depend’ is a BSD extension.

If a list of target ... is specified, make will build those targets. Otherwise a default target will be built: either a target explicitly marked with .MAIN or the first target encountered in the makefile.

Standard options are as follows:

Environment variables override macro assignments within makefiles.
mk
Read file mk instead of the default makefile. If mk is ‘-’, standard input is used. Multiple makefiles may be specified, and are read in the order specified.
Ignore non-zero exit of shell commands in the makefile. Equivalent to specifying ‘-’ before each command line in the makefile.
Continue processing after errors are encountered, but only on those targets that do not depend on the target whose creation caused the error.
Display the commands that would have been executed, but do not actually execute them.
Print a dump of the target rules and variables on stdout. Do not build anything.
Do not execute any commands, but exit with status 0 if the specified targets are up to date, and 1 otherwise.
Do not use the built-in rules specified in the system makefile, <sys.mk>.
Stop processing when an error is encountered. This is the default behavior. This is needed to negate the -k option during recursive builds.
Do not echo commands as they are executed. Equivalent to specifying ‘@’ before each command line in the makefile.
Rather than re-building a target as specified in the makefile, create it or update its modification time to make it appear up to date, a bit like touch(1).
NAME=value
Set the value of the variable NAME to value.

Extended options are as follows:

Try to be backwards compatible by executing the commands to make the prerequisites in a target rule in sequence. This is the default, in the absence of -j max_jobs.
directory
Enter directory before doing anything.
variable
Define variable to be 1.
flags
Turn on debugging, and specify which portions of make are to print debugging information. flags is one or more of the following:
A
Print all possible debugging information; equivalent to specifying all of the debugging flags.
a
Print debugging information about archive searching and caching.
c
Print debugging information about conditional evaluation.
d
Print debugging information about directory searching and caching.
D
Print warning messages about multiply defined command lists.
e
Print debugging information about expensive command heuristics.
f
Print debugging information about the expansion of for loops.
g1
Print the input graph before making anything.
g2
Print the input graph after making everything, or before exiting on error.
h
Print information about jobs being held back because of sibling/target groups races.
j
Print debugging information about forking processes to run commands.
k
Print debugging information about manually killing processes.
l
Print commands in Makefile targets regardless of whether or not they are prefixed by @. Also known as loud behavior.
m
Print debugging information about making targets, including modification dates.
n
Print debugging information about target names equivalence computations.
p
Help finding concurrency issues for parallel make by adding some randomization. If RANDOM_ORDER is defined, targets will be shuffled before being built. If RANDOM_DELAY is defined, make will wait between 0 and ${RANDOM_DELAY} seconds before starting a command. A given random seed can be forced by setting RANDOM_SEED, but this does not guarantee reproducibility.
q
‘quick death’ option: after a fatal error, instead of waiting for other jobs to die, kill them right away.
s
Print debugging information about inference (suffix) transformation rules.
t
Print debugging information about target list maintenance.
T
Print debugging information about target group determination.
v
Print debugging information about variable assignment.
directory
Specify a directory in which to search for makefiles and for "..."-style inclusions. Multiple directories can be added to form a search path. Furthermore, the system include path (see the -m option) will be used after this search path.
max_jobs
Specify the maximum number of jobs that make may have running at any one time. See the discussion about recursive invocations under BUGS.
directory
Specify a directory in which to search for system include files: sys.mk and <...>-style inclusions. Multiple directories can be added to form the system search path. Using -m will override the default system include directory /usr/share/mk.
variable
Print make's idea of the value of variable. Do not build any targets. Multiple instances of this option may be specified; the variables will be printed one per line, with a blank line for each null or undefined variable.

There are seven different types of lines in a makefile: dependency lines, shell commands, variable assignments, include statements, conditional directives, for loops, and comments. Of these, include statements, conditional directives and for loops are extensions.

A complete target rule is composed of a dependency line, followed by a list of shell commands.

In general, lines may be continued from one line to the next by ending them with a backslash (‘\’). The trailing newline character and initial whitespace on the following line are compressed into a single space.

Dependency lines consist of one or more targets, an operator, and zero or more prerequisites:

target ...:[prerequisite ...]

This creates a relationship where the targets “depend” on the prerequisites and are usually built from them. The exact relationship between targets and prerequisites is determined by the operator that separates them.

It is an error to use different dependency operators for the same target.

The operators are as follows:

A target is considered out of date if any of its prerequisites has been modified more recently than the target (that is, its modification time is less than that of any of its prerequisites). Thus, targets with no prerequisites are always out of date.

make will then execute the list of shell commands associated with that target.

Additional prerequisites may be specified over additional dependency lines: make will consider all prerequisites for determining out-of-date status. The target is removed if make is interrupted.

make first examines all prerequisites and re-creates them as necessary.

It will then always execute the list of shell commands associated with that target (as if the target always was out of date).

Like :, additional prerequisites may be specified over additional dependency lines, and the target is still removed if make is interrupted.

Each dependency line for a target is considered independently. A target is considered out of date for this target rule if any of its prerequisites in this dependency has been modified more recently than the target.

make will then execute the list of shell commands associated with that target. Target rules that specify no prerequisites are always executed.

The target will not be removed if make is interrupted.

The : operator is the only standard operator. The :: operator is a fairly standard extension, popularized by . The ! operator is a BSD extension.

As an extension, targets and prerequisites may contain the shell wildcard expressions ‘?’, ‘*’, ‘[]’ and ‘{}’. The expressions ‘?’, ‘*’ and ‘[]’ may only be used as part of the final component of the target or prerequisite, and must be used to describe existing files. The expression ‘{}’ need not necessarily be used to describe existing files. Expansion is in directory order, not alphabetically as done in the shell.

For maximum portability, target names should only consist of periods, underscores, digits and alphabetic characters.

The use of several targets can be a shorthand for duplicate rules. Specifically,

target1 target2: reqa reqa
	cmd1
	cmd2

may be replaced with

target1: reqa reqa
	cmd1
	cmd2
target2: reqa reqa
	cmd1
	cmd2

in general. But make is aware of parallel issues, and will not build those targets concurrently, if not appropriate.

Each target may have associated with it a series of shell commands, normally used to build the target. While several dependency lines may name the same target, only one of these dependency lines should be followed by shell commands, and thus define a complete target rule (unless the ‘::’ operator is used). Each of the shell commands in the target rule be preceded by a tab.

If a command line begins with a combination of the characters, ‘@’, ‘-’ and/or ‘+’, the command is treated specially:

‘@’
causes the command not to be echoed before it is executed.
‘-’
causes any non-zero exit status of the command line to be ignored.
‘+’
causes the command to be executed even if -n has been specified. (This can be useful to debug recursive Makefiles.)

Commands are executed using /bin/sh in "set -e" mode, unless ‘-’ is specified.

As an optimization, make may execute very simple commands without going through an extra shell process, as long as this does not change observable behavior.

make also maintains a list of valid suffixes through the use of the .SUFFIXES special target.

These suffixes can be used to write generic transformation rules called inference rules.

If a target has the form ‘.s1.s2’, where .s1 and .s2 are currently valid suffixes, then it defines a transformation from *.s1 to *.s2 (double suffix inference). If a target has the form ‘.s1’, where .s1 is a currently valid suffix, then it defines a transformation from *.s1 to * (single suffix inference).

A complete inference rule is a dependency line with such a target, the normal dependency operator, no prerequisites and a list of shell commands.

When make requires a target for which it has no complete target rule, it will try to apply a single active inference rule to create the target.

For instance, with the following Makefile, describing a C program compiled from sources a.c and b.c, with header file a.h:

.SUFFIXES: .c .o
.c.o:
	${CC} ${CFLAGS} -c $<

prog: a.o b.o
	${CC} ${CFLAGS} -o $@ a.o b.o

a.o b.o: a.h

b.o: b.c
	${CC} -DFOO ${CFLAGS} -o $@ $<

Consider b.o: there is a complete target rule re-creating it from b.c, so it will be compiled using ${CC} -DFOO.

Consider a.o: there is no explicit target rule, so make will consider valid transforms. Fortunately, there is an inference rule that can create a.o from a.c, so it will be compiled using ${CC}.

Note that extra prerequisites are still taken into account, so both a.o and b.o depend on a.h for re-creation.

Valid suffixes accumulate over .SUFFIXES lines. An empty .SUFFIXES can be used to reset the currently valid list of suffixes, but inference rules already read are still known by make, and they are marked as inactive. Redefining the corresponding suffix (or suffixes) will reactivate the rule.

In case of duplicate inference rules with the same suffix combination, the new rule overrides the old one.

For maximal portability, suffixes should start with a dot.

Variables in make are much like variables in the shell and, by tradition, consist of all upper-case letters. They are also called ‘macros’ in various texts. For portability, only periods, underscores, digits and letters should be used for variable names. The following operators can be used to assign values to variables:

Assign the value to the variable. Any previous value is overridden.
Assign with expansion, i.e., expand the value before assigning it to the variable (extension).
Append the value to the current value of the variable (extension).
Assign the value to the variable if it is not already defined (BSD extension). Normally, expansion is not done until the variable is referenced.
Perform variable expansion and pass the result to the shell for execution on the spot, assigning the result to the variable. Any newlines in the result are also replaced with spaces (BSD extension).
Perform variable expansion on the spot and pass the result to the shell for execution only when the value is needed, assigning the result to the variable.

This is almost identical to != except that a shell is only run when the variable value is needed. Any newlines in the result are also replaced with spaces (OpenBSD extension).

Any whitespace before the assigned value is removed; if the value is being appended, a single space is inserted between the previous contents of the variable and the appended value.

Several extended assignment operators may be combined together. For instance,

A ?!= cmd

will only run "cmd" and put its output into A if A is not yet defined.

Combinations that do not make sense, such as

A +!!= cmd

will not work.

Variables are expanded by surrounding the variable name with either curly braces (‘{}’) or parentheses (‘()’) and preceding it with a dollar sign (‘$’). If the variable name contains only a single letter, the surrounding braces or parentheses are not required. This shorter form is not recommended.

Variable substitution occurs at distinct times, depending on the type of line. Variables in dependency lines, conditional directives and include statements are expanded as the line is read. Variables in shell commands are expanded when the shell command is executed.

The four different classes of variables (in order of increasing precedence) are:

Environment variables
Variables defined as part of make's environment.
Global variables
Variables defined in the makefile or in included makefiles.
Command line variables
Variables defined as part of the command line.
Local variables
Variables that are defined specific to a certain target. Standard local variables are as follows:
@
The name of the target.
%
The name of the archive member (only valid for library rules).
!
The name of the archive file (only valid for library rules).
?
The list of prerequisites for this target that were deemed out of date.
<
The name of the prerequisite from which this target is to be built, if a valid inference rule (suffix rule) is in scope.
*
The file prefix of the file, containing only the file portion, no suffix or preceding directory components.

Those variables (and >) may be suffixed with a ‘D’ or a ‘F’, to yield the filename or directory part of the corresponding variables, e.g., ‘${@F}’ is equivalent to ‘${@:T}’ and ‘${@D}’ is equivalent to ‘${@:H}’.

For maximum compatibility, ‘<’ should only be used for actual inference rules. It is also set for normal target rules when there is an inference rule that matches the current target and prerequisite in scope. That is, in

.SUFFIXES: .c .o
file.o: file.c
	cmd1 $<

.c.o:
	cmd2

building file.o will execute "cmd1 file.c".

As an extension, make supports the following local variables:

>
The list of all prerequisites for this target.
.ALLSRC
Synonym for ‘>’.
.ARCHIVE
Synonym for ‘!’.
.IMPSRC
Synonym for ‘<’.
.MEMBER
Synonym for ‘%’.
.OODATE
Synonym for ‘?’.
.PREFIX
Synonym for ‘*’.
.TARGET
Synonym for ‘@’.

These variables may be used on the dependency half of dependency lines, when they make sense.

In addition, make sets or knows about the following internal variables, or environment variables:

$
A single dollar sign ‘$’, i.e., ‘$$’ expands to a single dollar sign.
.MAKE
The name that make was executed with (argv[0]).
.CURDIR
A path to the directory where make was executed.
.OBJDIR
Path to the directory where targets are built. At startup, make searches for an alternate directory to place target files. make tries to chdir(2) into MAKEOBJDIR (or obj if MAKEOBJDIR is not defined), and sets .OBJDIR accordingly. Should that fail, .OBJDIR is set to .CURDIR.
MAKEFILE_LIST
The list of files read by make.
.MAKEFLAGS
The environment variable MAKEFLAGS may contain anything that may be specified on make's command line. Its contents are stored in make's .MAKEFLAGS variable. Anything specified on make's command line is appended to the .MAKEFLAGS variable which is then entered into the environment as MAKEFLAGS for all programs which make executes.
MFLAGS
A shorter synonym for .MAKEFLAGS.
Alternate path to the current directory. make normally sets ‘.CURDIR’ to the canonical path given by getcwd(3). However, if the environment variable PWD is set and gives a path to the current directory, then make sets ‘.CURDIR’ to the value of PWD instead. PWD is always set to the value of ‘.OBJDIR’ for all programs which make executes.
.TARGETS
List of targets make is currently building.
MACHINE
Name of the machine architecture make is running on, obtained from the MACHINE environment variable, or through uname(3) if not defined.
MACHINE_ARCH
Name of the machine architecture make was compiled for, obtained from the MACHINE_ARCH environment variable, or defined at compilation time.
MACHINE_CPU
Name of the machine processor make was compiled for, obtained from the MACHINE_CPU environment variable, or defined at compilation time. On processors where only one endianness is possible, the value of this variable is always the same as MACHINE_ARCH.
MAKEFILE
Possibly the file name of the last makefile that has been read. It should not be used; see the BUGS section below.
.VARIABLES
List of all the names of global variables that have been set.

Variable expansion may be modified to select or modify each word of the variable (where “word” is a whitespace delimited sequence of characters). The general format of a variable expansion is as follows:

{variable[:modifier[:...]]}

Each modifier begins with a colon and one of the following special characters. The colon may be escaped with a backslash (‘\’).

Replaces each word in the variable with its suffix.
Replaces each word in the variable with everything but the last component.
Replaces each word in the variable with its lower case equivalent.
Replaces each word in the variable with its upper case equivalent.
pattern
Select only those words that match the rest of the modifier. The standard shell wildcard characters (‘*’, ‘?’, and ‘[]’) may be used. The wildcard characters may be escaped with a backslash (‘