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    Covered
    Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
    Downloads: 5 This Week
    Last Update:
    See Project
  • 2
    Tiria is a eclipse-plugin to view code coverage data (e.g. from cobertura) within the IDE. Main objective of the plugin is to show how the code coverage changes during project progress.
    Downloads: 0 This Week
    Last Update:
    See Project
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