Activity for Quite Universal Circuit Simulator

artsurd modified a comment on ticket #19

artsurd — Wed, 25 Mar 2026 20:54:03 -0000

Looks like the code was merged on GitHub https://github.com/Qucs/qucs/commit/4f8625ef32619a650ca78d1785e684077f5aac1d Which appears to have made it here too: https://sourceforge.net/p/qucs/git/ci/4f8625ef32619a650ca78d1785e684077f5aac1d/ Glad it made it in! I agree Codeberg is good. Zig went there as a middle finger to GitHub and Microslop. My own GitHub is mostly taken down now because of all the LLMs not respecting licenses. Have had a go with Gitea and Codeberg. It's nice in a way; git was made...

artsurd modified a comment on ticket #19

artsurd — Wed, 25 Mar 2026 20:46:21 -0000

artsurd modified a comment on ticket #19

artsurd — Wed, 25 Mar 2026 20:45:51 -0000

artsurd posted a comment on ticket #19

artsurd — Wed, 25 Mar 2026 20:45:08 -0000

Felix posted a comment on ticket #19

Felix — Wed, 25 Mar 2026 15:28:52 -0000

On Wed, Mar 25, 2026 at 01:29:27AM -0000, artsurd wrote: I haven't used SourceForge like this before, but thought I'd give it a go. I've also made the same request on GitHub in case this is the wrong place. Thanks. Since you raised it. I am not sure why the code was moved got github, probably just for the "git workflow". Today Codeberg might be a much better option, but I only recently created [1]. I will look at your patch when I find some time. [1] https://codeberg.org/qucs/gui

artsurd posted a comment on ticket #19

artsurd — Wed, 25 Mar 2026 01:29:26 -0000

GitHub PR: https://github.com/Qucs/qucs/pull/1116

artsurd modified a comment on ticket #19

artsurd — Wed, 25 Mar 2026 01:28:27 -0000

Here is the patch: From 4f8625ef32619a650ca78d1785e684077f5aac1d Mon Sep 17 00:00:00 2001 From: artsurd Date: Wed, 25 Mar 2026 01:08:00 +0000 Subject: [PATCH] Fix use after free in qucsMessageOutput --- qucs/main.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qucs/main.cpp b/qucs/main.cpp index 0a50bd8d6..8879f84eb 100644 --- a/qucs/main.cpp +++ b/qucs/main.cpp @@ -37,7 +37,9 @@ */ void qucsMessageOutput(QtMsgType type, const QMessageLogContext &, const...

artsurd posted a comment on ticket #19

artsurd — Wed, 25 Mar 2026 01:27:41 -0000

Here is the patch.

artsurd created ticket #19

artsurd — Wed, 25 Mar 2026 01:26:36 -0000

Fix use after free in qucsMessageOutput

Felix committed [d4c464] on Git

Felix — Sun, 11 Jan 2026 21:45:33 -0000

fix: Prevent segfault in Schematic::newMovingWires

Felix committed [5caab7] on Git

Felix — Tue, 06 Jan 2026 17:34:03 -0000

Merge 'lupdate'

Bernhard M. Wiedemann committed [d34888] on Git

Bernhard M. Wiedemann — Tue, 06 Jan 2026 17:34:03 -0000

Also check for lupdate-qt5

Felix committed [e995f9] on qucsator

Felix — Sun, 21 Dec 2025 11:49:58 -0000

add CONTRIBUTE

Felix committed [51e7d2] on qucsator

Felix — Sun, 21 Dec 2025 11:49:58 -0000

use default compiler in AC_PROG_CXX

phloks modified a comment on discussion Open Discussion

phloks — Thu, 04 Dec 2025 14:37:09 -0000

Please have a look at this schematic attached to this post. I have built this circuit in real ife, and it does what it is supposed to do. A low on ENABLE_TX_12V results in +12V on RX_12V, a high on ENABLE_TX_12V reslts in 0V on RX_12V. I tried to simulate this behaviour in QUCS, but could not get it right, Possibly model files for the 2N7002 and IRF4905 are wrong, so I replaced them with generic nMOS and pMOS devices available in QUCS. Simulation says it is successful, but in the graph nothing appears....

phloks posted a comment on discussion Open Discussion

phloks — Thu, 04 Dec 2025 14:36:08 -0000

Please have a look at this schematic attached to this post. I have built this circuit in real ife, and it does what it is supposed to do. A low on ENABLE_TX_12V results in +12V on RX_12V, a high on ENABLE_TX_12V reslts in 0V on RX_12V. I tried to simulate this behaviour in QUCS, but could not get it right, Possiblyy model files for the 2N7002 and IRF4905 are wrong, so I replaced them with generic nMOS and pMOS devices available in QUCS. Simulation says it is successful, but in the graph nothing appears....

Jesús Everardo Díaz Alvarado posted a comment on discussion Open Discussion

Jesús Everardo Díaz Alvarado — Sat, 29 Nov 2025 01:09:44 -0000

Hello everyone, My name is Jesús Everardo, and I am developing a Python module that acquires real-time S-parameters from the NanoVNA (S11/S21), performs frequency sweeps, and exports Touchstone and CSV files. I would like to integrate this functionality into Qucs/Qucs-S either as an extension, a measurement component, or an external interface to enable direct visualization and analysis of the measurements within the simulator. I would greatly appreciate any guidance on how to connect this data with...

Felix committed [f8f705] on Git

Felix — Thu, 23 Oct 2025 07:15:23 -0000

Merge Turkish translations update

GitHub committed [d26966] on Git

GitHub — Thu, 23 Oct 2025 07:15:23 -0000

Fix typo in translation for number of copies

GitHub committed [4e7bef] on Git

GitHub — Thu, 23 Oct 2025 07:15:23 -0000

Update Turkish translations in qtgeneric_tr.ts

GitHub committed [0771bb] on Git

GitHub — Thu, 23 Oct 2025 07:15:23 -0000

Refine Turkish translations in qtgeneric_tr.ts

Andre Larochelle posted a comment on discussion Open Discussion

Andre Larochelle — Tue, 22 Jul 2025 16:50:21 -0000

Is there a version for Apple Silicone. I have a Mac Mini M4.

Felix committed [efdec3] on Git

Felix — Fri, 27 Jun 2025 15:26:01 -0000

improve wire label dump/parse

Felix committed [772cbe] on Git

Felix — Fri, 27 Jun 2025 15:26:01 -0000

fix port access in position dump

Felix committed [9f59a7] on Git

Felix — Fri, 27 Jun 2025 15:26:01 -0000

fix position in graphics item dump

Felix committed [c38a9f] on Git

Felix — Thu, 26 Jun 2025 14:13:28 -0000

dump wire labels as nodes

Felix committed [993a3e] on Git

Felix — Thu, 26 Jun 2025 14:13:28 -0000

cleanup Schematic::dumpVerilogComponent

Felix committed [ded0d0] on Git

Felix — Thu, 26 Jun 2025 14:13:28 -0000

fix comment

Felix committed [cd9d7e] on Git

Felix — Thu, 26 Jun 2025 14:13:28 -0000

bump ref. missing connections

Felix committed [677270] on Git

Felix — Thu, 26 Jun 2025 14:13:27 -0000

Reading Verilog: Wire labels

Felix committed [1a8af8] on Git

Felix — Thu, 26 Jun 2025 14:13:27 -0000

Update Tests: Verilog Dump

Felix committed [1d9829] on Git

Felix — Thu, 26 Jun 2025 14:13:27 -0000

Verilog Dump: Dump Wire Label position

Felix committed [153cf4] on Git

Felix — Thu, 26 Jun 2025 14:13:27 -0000

net label test

Felix committed [9aeedd] on Git

Felix — Thu, 29 May 2025 09:50:58 -0000

fix indent. went wrong in 386426dd8eaf

David Lanzendörfer committed [d3a094] on Git

David Lanzendörfer — Thu, 29 May 2025 09:50:58 -0000

Removing unused code

Felix committed [18ba69] on Git

Felix — Thu, 29 May 2025 09:50:58 -0000

test status

David Lanzendörfer committed [386426] on Git

David Lanzendörfer — Thu, 29 May 2025 09:50:58 -0000

Parse attribut DRY fix

Felix committed [c5f5b5] on Git

Felix — Thu, 29 May 2025 09:50:57 -0000

Merge preamble

David Lanzendörfer committed [03439b] on Git

David Lanzendörfer — Thu, 29 May 2025 09:50:57 -0000

Introducing preample loading

David Lanzendörfer committed [60777d] on Git

David Lanzendörfer — Thu, 29 May 2025 09:50:57 -0000

Fix DRY violation

David Lanzendörfer committed [e5931e] on Git

David Lanzendörfer — Thu, 29 May 2025 09:50:57 -0000

Element "center and relative boundings" are private

Felix committed [54ba22] on Git

Felix — Thu, 15 May 2025 14:54:52 -0000

Merge experimental Verilog-S dump/load

David Lanzendörfer committed [1517fe] on Git

David Lanzendörfer — Thu, 15 May 2025 14:54:52 -0000

Verilog Parsing: Parse visibility

David Lanzendörfer committed [80b70f] on Git

David Lanzendörfer — Thu, 15 May 2025 14:54:52 -0000

Regenerating Verilog Schematics

Felix committed [217d40] on Git

Felix — Thu, 15 May 2025 14:54:52 -0000

create sch and vs round trip diffs during tests

Felix committed [3e4654] on Git

Felix — Thu, 15 May 2025 14:54:52 -0000

superficial testing

David Lanzendörfer committed [88292c] on Git

David Lanzendörfer — Thu, 15 May 2025 14:54:52 -0000

Verilog Schematic: Visibility of properties

David Lanzendörfer committed [e320dd] on Git

David Lanzendörfer — Thu, 15 May 2025 14:54:52 -0000

Paintings: Introducing setter and getter for attributes

Felix committed [702cd4] on Git

Felix — Thu, 15 May 2025 14:54:52 -0000

sync ctos with gnucap/develop & test

Felix committed [d12be2] on Git

Felix — Thu, 15 May 2025 14:54:52 -0000

fix S__text type

Felix committed [bb49da] on Git

Felix — Wed, 07 May 2025 07:08:31 -0000

ROADMAP, TODO update

Felix committed [a5285e] on Git

Felix — Mon, 05 May 2025 12:34:24 -0000

cleanup prj_log_compiler

David Lanzendörfer committed [83e055] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Verilog Dump: Painting/GraphicText dumping

David Lanzendörfer committed [67ba68] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Updating the Verilog schematics

Felix committed [2a731c] on Git

Felix — Mon, 05 May 2025 12:34:24 -0000

bugfix lang_verilog. always prefer qucs_type attribute

Felix committed [1d24b6] on Git

Felix — Mon, 05 May 2025 12:34:24 -0000

fix include in lang_verilog

Felix committed [814968] on Git

Felix — Mon, 05 May 2025 12:34:24 -0000

errors and warnings in component

David Lanzendörfer committed [3b4b5d] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Adding integrity check

David Lanzendörfer committed [50e06d] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Add label name getter method

David Lanzendörfer committed [d9cce3] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Write nodes out as wires

Felix committed [d8ad06] on Git

Felix — Mon, 05 May 2025 12:34:24 -0000

fix compile warnings, add Wire::port

David Lanzendörfer committed [4f7b74] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Add a warn method to Schematic

David Lanzendörfer committed [821275] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Add nodename_at function

David Lanzendörfer committed [3f791f] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Adding set_port_by index functionality

David Lanzendörfer committed [cb6483] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Bug fix: Solving save-as issue

David Lanzendörfer committed [d566e9] on Git

David Lanzendörfer — Mon, 05 May 2025 12:34:24 -0000

Bugfix: Open .vs files as schematic

Felix committed [15614b] on Git

Felix — Mon, 05 May 2025 12:34:24 -0000

fix qt rules in various qucs-*/Makefile.am

Felix committed [e58646] on Git

Felix — Thu, 10 Apr 2025 17:21:42 -0000

Merge 'comp_loading'

David Lanzendörfer committed [d33379] on Git

David Lanzendörfer — Thu, 10 Apr 2025 17:21:42 -0000

Using dump/parse identifier from Gnucap

Felix committed [6e908c] on Git

Felix — Thu, 10 Apr 2025 17:21:42 -0000

missing lib test

David Lanzendörfer committed [330d68] on Git

David Lanzendörfer — Thu, 10 Apr 2025 17:21:42 -0000

Positioning components without ports

Felix committed [fd3b63] on Git

Felix — Thu, 10 Apr 2025 17:21:42 -0000

more cleanup

David Lanzendörfer committed [655950] on Git

David Lanzendörfer — Thu, 10 Apr 2025 17:21:42 -0000

Move code over to correct compilation unit

Felix committed [059140] on Git

Felix — Thu, 10 Apr 2025 17:21:42 -0000

smart pointer conversion fix

Felix committed [f0dc33] on Git

Felix — Mon, 31 Mar 2025 10:03:02 -0000

Merge wire_cleanup

Felix committed [131502] on Git

Felix — Mon, 31 Mar 2025 10:03:02 -0000

cleanup node interface a bit

Felix committed [b287c4] on Git

Felix — Mon, 31 Mar 2025 10:03:02 -0000

missing test file

Felix committed [b4969f] on Git

Felix — Mon, 31 Mar 2025 10:03:02 -0000

split off LegacyComponent

Felix committed [319ea4] on Git

Felix — Mon, 31 Mar 2025 10:03:02 -0000

move up "Component" class

Felix committed [bf01f1] on Git

Felix — Mon, 31 Mar 2025 10:03:02 -0000

prepare Wire ports cleanup

Felix committed [0b98b9] on Git

Felix — Sun, 30 Mar 2025 12:32:27 -0000

hello world ngspice

Felix committed [a28d41] on Git

Felix — Sun, 30 Mar 2025 12:32:27 -0000

hello world example

Felix committed [eb405c] on Git

Felix — Sun, 30 Mar 2025 12:32:27 -0000

more Verilog_File cleanup and disentangle

Felix committed [469c2f] on Git

Felix — Sun, 30 Mar 2025 12:32:27 -0000

"Verilog" device. initial fixes

Felix committed [ab9f0d] on Git

Felix — Sun, 30 Mar 2025 12:32:27 -0000

some more parameters are attributes

Felix committed [a716ea] on Git

Felix — Sun, 30 Mar 2025 12:32:27 -0000

Makefile fixes

Felix committed [3f02b9] on Git

Felix — Sat, 29 Mar 2025 17:35:11 -0000

Merge wire placement

David Lanzendörfer committed [23556f] on Git

David Lanzendörfer — Sat, 29 Mar 2025 17:35:11 -0000

Initial code for wire placement

David Lanzendörfer committed [8a8777] on Git

David Lanzendörfer — Sat, 29 Mar 2025 17:35:11 -0000

Component placement

Felix committed [adae75] on Git

Felix — Sat, 29 Mar 2025 17:35:11 -0000

Merge 'lib'

Felix committed [0fbf6d] on Git

Felix — Sat, 29 Mar 2025 17:35:11 -0000

cleanup/fix Sub

Felix committed [a91de9] on Git

Felix — Sat, 29 Mar 2025 17:35:11 -0000

cleanup/fix Lib

Felix committed [45e870] on Git

Felix — Wed, 26 Mar 2025 20:11:15 -0000

Felix committed [7d8a06] on Git

Felix — Wed, 26 Mar 2025 20:11:15 -0000

Merge read_verilog

Felix committed [d7333c] on Git

Felix — Wed, 26 Mar 2025 20:11:15 -0000

fix parameter parsing

Felix committed [7d825f] on Git

Felix — Wed, 26 Mar 2025 20:11:15 -0000

fix out of range Props access, try #2

David Lanzendörfer committed [992a41] on Git

David Lanzendörfer — Wed, 26 Mar 2025 20:11:15 -0000

Solve crash when dumping netlists/fix refs

Felix committed [bba8c1] on Git

Felix — Wed, 26 Mar 2025 20:11:15 -0000

fix compile warnings

Felix committed [fe4562] on Git

Felix — Wed, 26 Mar 2025 20:11:14 -0000

Solving uninitialized value warning

Felix committed [495080] on Git

Felix — Wed, 26 Mar 2025 20:11:14 -0000

cleanup, disentangle dumpDeclaration