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EDA & Design

EDA tools, chip design IP, verification, and design-to-tapeout coverage.

NVIDIA's cuPotential Takes the CUDA Moat Down to the Atom in the AI-Defined Fab
Analysis

NVIDIA’s cuPotential Takes the CUDA Moat Down to the Atom in the AI-Defined Fab

NVIDIA’s cuPotential launch extends CUDA-X to molecular dynamics as AI-defined fabs gain adopters across Lam, KLA, Synopsys, and Applied.

Brendan Burke · Oct 14, 2026 · 9 min

OpenAI and Synopsys Partner to Develop AI Model for Chip Design
AI Silicon

OpenAI and Synopsys Partner to Develop AI Model for Chip Design

OpenAI and Synopsys announced a multi-year strategic partnership to develop GPT-Synopsys, a specialized artificial intelligence model designed to automate and optimize semiconductor design workflows. The agreement combines OpenAI’s advanced AI models with Synopsys’ electronic design automation (EDA) software and semiconductor engineering expertise. OpenAI will license Synopsys’ EDA tools to develop the specialized model, with the […]

Andy Patrizio · Oct 13, 2026 · 2 min

Quantum Phononic Links Could Help Scale Chips to Higher Qubit Levels
AI Silicon

Quantum Phononic Links Could Help Scale Chips to Higher Qubit Levels

Researchers have developed a quantum chip architecture that uses vibrations called phonons to connect qubits across long distances, potentially addressing a key obstacle to building large-scale quantum computers. The technology, Quantum Phononic Links (QPLs), is designed to allow qubits that are physically separated to exchange quantum information. The researchers say the approach can support connections […]

James Maguire · Oct 6, 2026 · 2 min

Synopsys Investor Day 2026 Turns EDA Into a Royalty and AI Model Revenue Share Business
Analysis

Synopsys Investor Day 2026 Turns EDA Into a Royalty and AI Model Revenue Share Business

Synopsys Investor Day 2026 raises long-term growth to mid-teens as a $1B Amazon AOIP royalty deal and GPT-Synopsys with OpenAI reprice EDA economics.

Brendan Burke · Oct 2, 2026 · 8 min

Synopsys Autopilot Aims to Consolidate Chip Design Around One Stack
Analysis

Synopsys Autopilot Aims to Consolidate Chip Design Around One Stack

Synopsys Autopilot and seven AgentEngineer agents push toward full-lifecycle chip design automation with 2x token efficiency.

Brendan Burke · Sep 28, 2026 · 9 min

TSMC's OIP Forum Turns Agentic Chip Design Demos Into Production Flows
Analysis

TSMC’s OIP Forum Turns Agentic Chip Design Demos Into Production Flows

TSMC OIP 2026 brought A14 certifications and foundry-endorsed agentic EDA flows, while IC-Link by imec opened managed-cloud access to advanced nodes.

Brendan Burke · Sep 24, 2026 · 7 min

Germany and Netherlands Invest €40 Million to Accelerate AI Chip Design
AI Silicon

Germany and Netherlands Invest €40 Million to Accelerate AI Chip Design

Germany and the Netherlands have launched a €40 million initiative to develop AI-powered semiconductor design technology, seeking to strengthen Europe’s chip industry and reduce its reliance on U.S. technology. The new joint initiative brings together Germany’s Federal Agency for Breakthrough Innovation (SPRIND) and the Netherlands’ National Agency for Disruptive Innovation (NADI). The agencies will fund […]

James Maguire · Sep 23, 2026 · 2 min

Cadence ChipStack Adds RTL Generation: Can Agents Code Production Silicon?
Analysis

Cadence ChipStack Adds RTL Generation: Can Agents Code Production Silicon?

Cadence ChipStack RTL Generation Agent claims 24% area and 18% power savings over foundation model code, with Honda validating on automotive SoCs.

Brendan Burke · Sep 23, 2026 · 7 min

ADI SHARC-FX Runs on Cadence IP: Is the Proprietary DSP Era Over?
Analysis

ADI SHARC-FX Runs on Cadence IP: Is the Proprietary DSP Era Over?

ADI SHARC-FX rebuilds the SHARC automotive audio DSP on Cadence Tensilica IP, trading a proprietary ISA for 5X performance and on-chip AI.

Brendan Burke · Sep 23, 2026 · 6 min

AMD MLPerf Inference 6.1 Results Show ROCm Gaining 38% on the Same MI355X Hardware
Analysis

AMD MLPerf Inference 6.1 Results Show ROCm Gaining 38% on the Same MI355X Hardware

AMD’s MLPerf Inference 6.1 gains of up to 38% on fixed MI355X hardware set the baseline for tracking ROCm’s six-week release cadence going forward.

Brendan Burke · Sep 16, 2026 · 10 min

Rapidus’ IIM-1 Fab Construction is Completed. Will Cadence Make It the First Agentic Foundry?
Analysis

Rapidus’ IIM-1 Fab Construction is Completed. Will Cadence Make It the First Agentic Foundry?

Rapidus’ IIM-1 Fab finishes construction and enters process testing, with Cadence-integrated Raads agentic design tools and IBM transistor IP in tow.

Brendan Burke · Aug 31, 2026 · 8 min

AMD Acquires Taalas to Advance AI Workload Optimization
Analysis

AMD Acquires Taalas to Advance AI Workload Optimization

AMD acquires Taalas and its two-month model-to-silicon design flow, adding ex-AMD architects as agentic EDA collapses the cost of a chip design start.

Brendan Burke · Aug 7, 2026 · 8 min

Synopsys, Cadence, and Siemens Take Agentic Chip Design Autonomous at DAC
Analysis

Synopsys, Cadence, and Siemens Take Agentic Chip Design Autonomous at DAC

NVIDIA and AMD anchor agentic chip design at DAC 2026 as Synopsys, Cadence, and Siemens ship autonomous EDA workflows on their platforms.

Brendan Burke · Aug 5, 2026 · 7 min

Arteris, Arm Partner for Secure Chip Development
AI Silicon

Arteris, Arm Partner for Secure Chip Development

Semiconductor IP company Arteris is expanding its longstanding partnership with Arm Holdings to provide advanced hardware security verification across a broader range of Arm’s CPU portfolio. With so many technologies, the development cycle is focused on getting it running, making it run faster and then securing it, in that order. Security has a tendency to […]

Andy Patrizio · Jul 16, 2026 · 2 min

Cadence AuraStack Extends Agentic Leadership Toward Advanced Packaging Design
Analysis

Cadence AuraStack Extends Agentic Leadership Toward Advanced Packaging Design

Cadence AuraStack AI Super Agent extends agentic leadership into PCB and advanced packaging design, addressing multiphysics bottlenecks in rack-scale AI.

Brendan Burke · Jul 16, 2026 · 6 min

Synopsys Q1 FY 2026 Earnings Highlight EDA and Ansys Momentum
Analysis

Synopsys Q1 FY 2026 Earnings Highlight EDA and Ansys Momentum

Synopsys Q1 earnings show strong AI-led design automation demand, Ansys momentum, and disciplined execution supporting full-year guidance.

Brendan Burke · May 28, 2026 · 6 min

Cadence Q4 FY 2025 Earnings Underscore AI-Led EDA Momentum
Analysis

Cadence Q4 FY 2025 Earnings Underscore AI-Led EDA Momentum

Cadence Q4 FY 2025 shows AI-led EDA momentum, hardware strength, and record backlog; agentic AI and hyperscaler supporting FY 2026 guidance.

Brendan Burke · May 28, 2026 · 5 min

Arm AGI CPU Goes to Market via Supermicro and Verda at 2026 OCP EMEA Summit
Analysis

Arm AGI CPU Goes to Market via Supermicro and Verda at 2026 OCP EMEA Summit

Agentic AI infrastructure advances as Supermicro and Verda leverage OCP standards to integrate Arm AGI CPUs with NVIDIA GPUs at scale.

Brendan Burke · May 28, 2026 · 5 min

Can Synopsys and NVIDIA Redefine Chip Design Timelines with 30x Speed Gains?
Analysis

Can Synopsys and NVIDIA Redefine Chip Design Timelines with 30x Speed Gains?

Synopsys and NVIDIA chip design collaboration boosts EDA simulation speeds up to 30x with Grace Blackwell, CUDA-X, and NIM microservices.

Richard Gordon · May 28, 2026 · 4 min

CadenceLIVE 2026 — Can Agentic AI Finally Crack 3D IC Design Automation?
Analysis

CadenceLIVE 2026 — Can Agentic AI Finally Crack 3D IC Design Automation?

CadenceLIVE 2026 expands Cadence agentic AI chip design with ViraStack and InnoStack; 3D IC automation remains the toughest frontier.

Guy Currier · May 28, 2026 · 9 min